Memory devices can use a voltage difference between differential bitlines to sense the current state of a memory cell. For designs with small differential bitline levels, the output noise can feedback onto the bitlines and may collapse the bitline and TBUS differential signal levels. Due to the collapsed TBUS differential signal, an incorrect state could be sensed by the sense amplifier which can cause an output glitch, or even multiple output glitches. Static bitline load designs have poor noise immunity for small bitline voltage swings. The bitline voltage swing is presented to the TBUS through a switch.
Referring to FIG. 1, a circuit 10 illustrates a static bitline load design block diagram. The circuit 10 comprises an address path block 12, a memory array block 14, a sense amplifier block 16 and an output path block 18. The address path block 12 presents a wordline signal WL in response to an address signal. The memory array block 14 presents a signal TBUS in response to the signal WL. The sense amplifier block 16 presents a signal SAOUT in response to the signal TBUS. The output path block 18 presents a signal OUTPUT in response to the signal SAOUT.
Referring to FIG. 2, a timing diagram of the signals of FIG. 1 is shown. A signal ADDRESS has a transition 20 that indicates an external address has changed state. The signal WL has a positive transition 22 that responds to the transition 20 of the signal ADDRESS. The signal TBUS has a transition 24 that responds to the positive transition 22 of the signal WL. The signal SAOUT has a transition 26 that responds to the transition 24 of the signal TBUS. The signal OUTPUT has a transition 28 that responds to the transition 26 of the signal SAOUT. The signal TBUS has a transition 30 that responds to the transition 28 of the signal OUTPUT. The transition 30 can cause a series of transitions in the signal SAOUT and the signal OUTPUT that may ultimately lead to the sensing of incorrect data. For example, the signal SAOUT has a transition 32 that responds to the transition 30 of the signal TBUS. The signal OUTPUT has a transition 34 that responds to the transition 32 of the signal SAOUT. After a state 35, the signal TBUS has a transition 36 where the TBUS recovers to the correct state. The signal SAOUT has a transition 38 that responds to the transition 36 of the signal TBUS. The signal OUTPUT has a transition 40 that responds to the transition 38 of the signal SAOUT. The signal OUTPUT presents incorrect data between the transition 34 and the transition 40. Furthermore, a collapse of the signal TBUS may occur at a point 42 in response to the transition 34.
A conventional approach to eliminating TBUS sensitivity to output noise is to utilize large bitline swings and use address transition detection circuitry. While such a design may provide better noise immunity than the circuit of FIG. 1, it has other undesirable effects such as limiting the ultimate size of the array due to current constraints.
Referring to FIG. 3, a circuit 50 is shown illustrating such a conventional approach. The circuit 50 comprises an address path block 52, a memory array block 54, a sense amplifier block 56, an output path block 58, an address transition detect block 60 and a control block 62. The address path block 52 presents a signal WL, the memory array block 54 presents a signal TBUS, the sense amplifier block 56 presents a signal SAOUT, the output path block 58 presents a signal OUTPUT, the address transition detect block 60 presents a signal ATD and the control block 62 presents a signal PRCHG and a signal SAEN.
Referring to FIG. 4, a timing diagram of the various signals of FIG. 3 is shown. An external address signal ADDRESS has a transition 64. The signal WL has a transition 66 that responds to transition 64 of the signal ADDRESS. The signal ATD has a positive transition 68 that responds to a transition 64 of the signal ADDRESS. The signal PRCHG has a positive transition 70 that responds to the positive transition 68 of the signal ATD. The signal SAEN has a negative transition 72 that responds to the positive transition 68 of the signal ATD. The signal TBUS has a transition 74 that responds to the positive transition of the signal PRCHG. The signal PRCHG also has a negative transition 76. The signal TBUS has a transition 78 that responds to the negative transition 76 of the signal PRCHG. The signal SAEN has a positive transition 80 that responds to the negative transition 76 of the signal PRCHG. The signal SAOUT has a transition 82 that responds to the positive transition 80 of the signal SAEN. The signal OUTPUT has a transition 84 that responds to the transition 82 of the signal SAOUT. The signal TBUS has a reduced differential portion 87 that responds to the transition 84 of the signal OUTPUT. The signal ADDRESS has a second transition 86. The signal ATD has a positive transition 88 that responds to the transition 86 of the signal ADDRESS. The signal WL has a transition 90 that also responds to the transition 86 of the signal ADDRESS. The signal PRCHG has a positive transition 92 that responds to the positive transition 88 of the signal ATD. The signal TBUS has a transition 94 that responds to the positive transition 92 of the signal PRCHG. The signal PRECHG also has a negative transition 96. The signal TBUS has a transition 98 that responds to the negative transition 96 of the signal PRCHG. The signal SAEN has a negative transition 100 that responds to the positive transition 88 of the signal ATD. The signal SAEN has a positive transition 102 that responds to the negative transition 96 of the signal PRCHG. The signal SAOUT has a transition 104 that responds to the positive transition 102 of the signal SAEN. The signal OUTPUT has a transition 106 that responds to the transition 104 of the signal SAOUT.
Additional conventional approaches may include using an output buffer reference control circuit. Such a reference control circuit may trade off noise control with speed. However, such a reference control circuit may be difficult to design over process corners. Glitch filters may be implemented as another approach to providing noise immunity. However, such glitch filters may have a negative impact on the speed of the device. The addition of split-power busses to isolate noisy power supplies may be implemented as another approach. However, such split-power busses increase the overall die size as well as make the overall power bussing more complex.